Bipolar and MOSFET’s Equations
Regions of BJT operation
The transistor is off. There is no conduction between the collector and the emitter. (IB = 0 therefore IC = 0)
The transistor is on. The collector current is proportional to and controlled by the base current (IC = βIB) and relatively insensitive to VCE. In this region the transistor can be an amplifier.
The transistor is on. The collector current varies very little with a change in the base current in the saturation region. The VCE is small, a few tenths of a volt. The collector current is strongly dependent on VCE unlike in the active region. It is desirable to operate transistor switches in or near the saturation region when in their on state.
Rules for Bipolar Junction Transistors (BJTs)
For an npn transistor, the voltage at the collector VC must be greater than the voltage at the emitter VE by at least a few tenths of a volt; otherwise, current will not flow through the collector-emitter junction, no matter what the applied voltage at the base. For pnp transistors, the emitter voltage must be greater than the collector voltage by a similar amount.
For the npn transistor, there is a voltage drop from the base to the emitter of 0.6 V. For a pnp transistor, there is also a 0.6 V rise from the base to the emitter. In terms of operation, this means that the base voltage VB of an npn transistor must be at least 0.6 V greater that the emitter voltage VE; otherwise, the transistor will not pass emitter-to-collector current. For a pnp transistor, VB must be at least 0.6 V less than VE; otherwise, it will not pass a
This chapter covers various aspects of the CMOS process from a physical point of view. In order to understand CMOS technology, a brief review of the basic semiconductor fabrication processes is presented, followed by a description of the fabrication steps required to build the basic CMOS process. Next, the PN junction is presented and analyzed, followed by a description of how active and passive components compatible with the CMOS technology are built. Next, important limitations on the performance of CMOS technology including latch-up, temperature dependence, and noise are covered.
Mixed-Signal IC Design Flow
1. Domain-specific design
2. Mixed-signal analysis
3. Physical design
Post layout simulation
Place and route
4. Full chip assembly & physical verification
5. Mixed-signal functional verification