This chapter covers various aspects of the CMOS process from a physical point of view. In order to understand CMOS technology, a brief review of the basic semiconductor fabrication processes is presented, followed by a description of the fabrication steps required to build the basic CMOS process. Next, the PN junction is presented and analyzed, followed by a description of how active and passive components compatible with the CMOS technology are built. Next, important limitations on the performance of CMOS technology including latch-up, temperature dependence, and noise are covered.
Mixed-Signal IC Design Flow
1. Domain-specific design
1.1 Analog/RF
Schematic capture
Analog simulation
1.2 Digital
Design entry
Behavioral simulation
2. Mixed-signal analysis
3. Physical design
Analog/RF
Physical layout
Physical verification
Post layout simulation
3.1 Digital
Synthesis
Place and route
Functional verification
4. Full chip assembly & physical verification
5. Mixed-signal functional verification
6. Tape-out
